Opcode/Instruction | Op / En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
---|---|---|---|---|

F2 0F 51/r SQRTSD xmm1,xmm2/m64 | A | V/V | SSE2 | Computes square root of the low double-precision floating-point value in xmm2/m64 and stores the results in xmm1. |

VEX.LIG.F2.0F.WIG 51/r VSQRTSD xmm1,xmm2, xmm3/m64 | B | V/V | AVX | Computes square root of the low double-precision floating-point value in xmm3/m64 and stores the results in xmm1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. |

EVEX.LLIG.F2.0F.W1 51/r VSQRTSD xmm1 {k1}{z}, xmm2, xmm3/m64{er} | C | V/V | AVX512F | Computes square root of the low double-precision floating-point value in xmm3/m64 and stores the results in xmm1 under writemask k1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. |

Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |

A | NA | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |

B | NA | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | NA |

C | Tuple1 Scalar | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | NA |

Computes the square root of the low double-precision floating-point value in the second source operand and stores the double-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM registers.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. The quadword at bits 127:64 of the destination operand remains unchanged. Bits (MAXVL-1:64) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding bits of the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.

EVEX encoded version: The low quadword element of the destination operand is updated according to the writemask.

Software should ensure VSQRTSD is encoded with VEX.L=0. Encoding VSQRTSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.

IF (EVEX.b = 1) AND (SRC2 *is register*) THEN SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); FI; IF k1[0] or *no writemask* THEN DEST[63:0] := SQRT(SRC2[63:0]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged* ELSE ; zeroing-masking THEN DEST[63:0] := 0 FI; FI; DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0

DEST[63:0] := SQRT(SRC2[63:0]) DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0

DEST[63:0] := SQRT(SRC[63:0]) DEST[MAXVL-1:64] (Unmodified)

VSQRTSD __m128d _mm_sqrt_round_sd(__m128d a, __m128d b, int r);

VSQRTSD __m128d _mm_mask_sqrt_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int r);

VSQRTSD __m128d _mm_maskz_sqrt_round_sd(__mmask8 k, __m128d a, __m128d b, int r);

SQRTSD __m128d _mm_sqrt_sd (__m128d a, __m128d b)

Invalid, Precision, Denormal

Non-EVEX-encoded instruction, see Table 2-20, “Type 3 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions”.