# GF2P8AFFINEQB
— Galois Field Affine Transformation

Opcode/Instruction |
Op/En |
64/32 bit Mode Support |
CPUID Feature Flag |
Description |

66 0F3A CE /r /ib GF2P8AFFINEQB xmm1, xmm2/m128, imm8 |
A |
V/V |
GFNI |
Computes affine transformation in the finite field GF(2^8). |

## Instruction Operand Encoding
¶

Op/En |
Tuple |
Operand 1 |
Operand 2 |
Operand 3 |
Operand 4 |

A |
NA |
ModRM:reg (r, w) |
ModRM:r/m (r) |
imm8 (r) |
NA |

### Description
¶

The AFFINEB instruction computes an affine transformation in the Galois Field 2^{8}. For this instruction, an affine transformation is defined by A * x + b where “A” is an 8 by 8 bit matrix, and “x” and “b” are 8-bit vectors. One SIMD register (operand 1) holds “x” as either 16, 32 or 64 8-bit vectors. A second SIMD (operand 2) register or memory operand contains 2, 4, or 8 “A” values, which are operated upon by the correspondingly aligned 8 “x” values in the first register. The “b” vector is constant for all calculations and contained in the immediate byte.

The SSE encoded forms of the instruction require16B alignment on their memory operations.

### Operation
¶

define parity(x):
t ← 0 // single bit
FOR i ← 0 to 7:
t = t xor x.bit[i]
return t
define affine_byte(tsrc2qw, src1byte, imm):
FOR i ← 0 to 7:
* parity(x) = 1 if x has an odd number of 1s in it, and 0 otherwise.*
retbyte.bit[i] ← parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
return retbyte

#### GF2P8AFFINEQB srcdest, src1, imm8 (128b SSE encoded version)
¶

FOR j ← 0 TO 1:
FOR b ← 0 to 7:
SRCDEST.qword[j].byte[b] ← affine_byte(SRC1.qword[j], SRCDEST.qword[j].byte[b], imm8)

### Intel C/C++ Compiler Intrinsic Equivalent
¶

GF2P8AFFINEQB __m128i _mm_gf2p8affine_epi64_epi8(__m128i, __m128i, int);

GF2P8AFFINEQB __m128i _mm_mask_gf2p8affine_epi64_epi8(__m128i, __mmask16, __m128i, __m128i, int);

GF2P8AFFINEQB __m128i _mm_maskz_gf2p8affine_epi64_epi8(__mmask16, __m128i, __m128i, int);

### SIMD Floating-Point Exceptions
¶

None.

### Other Exceptions
¶

Legacy-encoded: Exceptions Type 4.